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Product Name:KHF-E5 CPLD/FPGA Development Lab System
Product Series:Microprocessor and its Application (MCU, CPLD/FPGA, ARM, DSP) Series
Product Introduction

Technical Description
    • Configuration: the Altera (ACEX 1K low voltage series)downloading board for IC is equipped, it also compatibles downloading board for IC of Lattice and Xilinx companies.
    • FPGA ACEX 1K100 kernel board: it includes 4992 macro logical cells, namely 10 million gates. 12 embedded RAM modules (capacity: 4kbit for each RAM module, 208 pins).
    • CPLD EPM3256 kernel board (optional): 256 macrocells, namely 12000 gates (208 pins).
        Lattice LFXP6C and Xilinx XC3S250 are optional.
    • ispPAC10 analog programmable device is equipped (ispPAC20 and ispPAC80 are optional), only digital circuits experiment is available to carry out.
    • Variable languages: to master the usage of hardware description languages: AHDL, VHDL, Verilog-HDL etc.
    • Main board
    • 10 LEDs (6 parallel scanning LED and 4 serial scanning LED)
    • 16 digital switches and 4 pulse switches (KP1-KP4), both of them active in low level. A positive pulse is generated when pulse switch is pressed down if data switch actives low level, vice versa.
    • A/D conversion, double AD conversion is adopted and 8-bit A/D converter: ADC0809 is adopted. 
    • D/A converter, the DAC0832 is adopted.
    • Universal keypad: 16 tactile switches(4X4)
    • MCU expansion slot (40 pin)
    • Peripheral extension slot: 40PIN extension slot.
    • 128×64 character LCD module, 16×16 dot matrix module.
    • Voice input/output modules with audio power amplifier circuit and RAM circuit.
    • VGA interface, USB interface, PS/2 interface and parallel communication interface.
    Comment: Other multi-curriculum experiments such as: MCU-based, analog circuits, communication principle and digital system design are available to carry out through proper design.
Specification
    • Power supply: single-phase 220V±10% 50Hz    
    • Environment temperature:  -10℃~+40℃
    • Power capacity: <0.2kVA
Experiments
    • Simple Logic Circuit
    • Decoder and Register Circuit
    • Full Adder
    • Frequency Dividing and 12-to-1 Circuits
    • Digital Clock (using Hardware Description Language)
    • Dynamic Scanning Display Circuit
    • Complex Digital Clock and Scanning Display
    • BCD Conversion Circuit
    • Data Acquisition and Display Circuit
    • 8-bit Divider
    • Moore State Machine
    • 4×4 Array Keyboard Scanning Display
    • LPM and 8×8 Multiplier
    • Function Waveform Generator (using FPGA)
    • Serial communication of FPGA (half duplex)
    • Digital system design and MCU interface (1)-shift register
    • Digital system design and MCU interface (2)-read/write to the external RAM using MCU
    • Digital system design and MCU interface (3)-A/D conversion
    • Digital system design and MCU interface (4)-D/A conversion
    • Digital system design and MCU interface (5)-keypad interface
    • Duplex Communication between FPGA and PC
    • Parallel Communication between FPGA and PC
    • Musical performance circuit
    • Music Playing Circuit
    • Music Editing Circuit
    • VGA Display
    • Dot Array Display
    • LCD Display
    • PS2 Interface
    • USB Interface
    • Signal Generator
    • Arbitrary Waveform Generator
    • Digital Frequency Meter
    • Communication error coding/decoding and pseudo-noise coding
    • FIR Low-pass Filter Design
    • FIR high-pass Filter Design
    • ispPAC10 Gain Adjustment
    • ispPAC10 Interface and Application
    • ispPAC10 Second-order Filter
    • ispPAC10 Ladder Filter
    • Bridge Measurement (using ispPAC10)
    • Temperature Measurement (using ispPAC10)
    • Voltage Monitoring (using ispPAC20)
    • ispPAC20 Signal Amplifying and Comparation
    • Temperature Measurement (using ispPAC20)
    • ispPAC80 Programmable Filter
    • ispPAC80 Programmable Low-pass Filter

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